In the prior art, a pellet check for a semiconductor memory under a wafer state was carried out with a memory tester by performing a writing and a reading-out of data in respect to each of the chips on the wafer in the same manner as that of the actual operation. In this pellet checking operation, more practically, each of the probes of the probe card connected to the memory tester was at first contacted with a terminal of its corresponding semiconductor memory, a predetermined address signal was given to the address input memory of the semiconductor memory, a control signal was applied to the control signal input terminal of the semiconductor memory, the data from the driver of the memory tester was applied to the input-output terminal of the semiconductor memory so as to write data into the memory cell of the semiconductor memory. Then, the data was read out, a potential at the input-output terminal of the semiconductor memory was compared with a reference voltage by a comparator in the memory tester, thereby the output data in the semiconductor memory was reproduced, it was discriminated whether or not the written data and the read-out data are coincided to each other for every input-output terminal of the semiconductor memory and further it was discriminated whether or not the writing and the reading-out were normal or not.
In turn, in the memory tester, the number of drivers and comparators are set in response to its type and the number of concurrent measurements of chips in the pellet check is widely influenced by the number of terminals in the semiconductor memory. In the pellet check of the prior art semiconductor memory, there was a problem that as the number of terminals in the semiconductor memory is increased, the number of concurrent measurements was decreased and a measuring cost was expensive. In addition, since a number of drivers and comparators were needed in the memory tester, it was also difficult to perform a wafer burn-in test for performing a burn-in test for all the chips in the wafer under its wafer state.
In addition, referring now to FIG. 1 showing an example of configuration of SRAM (Static Random Access Memory), a power supply is supplied in parallel to the memory cell array 101 and the peripheral circuit 102 through the power supply pad 103 and the ground pad 104. It is sometimes found that the current supply part is provided with a down-converter and an up-converter (a power supply voltage-drop circuit and a power supply increasing circuit) and the like and in this case, they are installed among the power supply pad 103, the memory cell array 101 and the peripheral circuit 102.
In the case that a number of semiconductor chips are measured in parallel to each other, current is supplied concurrently from the memory tester to many chips within the same wafer. At this time, if there is a chip having a power supply terminal and a ground terminal short-circuited from each other in the wafer, an excessive load is applied to the current supply part of the tester and a stable measurement is prohibited. In particular, there occurs a problem in the case that many chips in the same wafer are concurrently tested for wafer burn-in test. In order to avoid this problem, it is necessary to arrange many relays at a current supply part when an accommodation is set at the tester for shutting off the power supply in the failure chip and this becomes a cause of increasing cost for the tester.